1. Field of the Invention
The present invention relates to a microprocessor environment, wherein a plurality of peripheral devices are connected to a microprocessor (CPU), the microprocessor writing data to and reading data from the peripheral devices. To be more specific, the present invention relates to a method circuit arrangement for implementing timing between a microprocessor and its peripheral devices.
2. Description of the Related Art
FIG. 1 shows a hardware environment as described above, wherein four different (having different speeds) peripheral devices A . . . D are connected to a microprocessor 10 by means of its data bus 11 and address bus 12 in a manner known per se. (It should be noted that in the figures presented below, the signal lines are connected to one another only at those points which are indicated by small circles) . In this exemplifying case, the peripheral device A is a medium-speed (one wait state) EPROM, the peripheral device B is a high-speed (no wait states) SRAM (Static Random Access Memory), the peripheral device C is a low-speed (two wait states) peripheral device, and the peripheral device D is a very low-speed (three wait states) peripheral device. It is also assumed that the address hold time of the peripheral device C is two clock cycles, and that the address hold time of the peripheral device D is three clock cycles. (Address hold time will be defined below). The peripheral devices C and D may be for instance serial input-output controllers or A/D converters.
The wait state mentioned above, which represents the speed of a peripheral device, means that a microprocessor extends the assertion period of signals according to the assertion of a corresponding control signal (if the control signal is not asserted, the microprocessor operates as quickly as it is able to). The control signal is usually referred to as a WAIT signal, and in this exemplifying case, this signal is generated in a decoder 13, wherefrom it is applied to the microprocessor. (In some processors, for instance in processors manufactured by Motorola, a corresponding function is implemented with a signal referred to as ACKNOWLEDGE). In the manner described above, it is thus possible to adjust a microprocessor to wait for slower peripheral devices.
The signals used in FIG. 1 have the meanings represented in the following table. The reference of a signal is formed from its generally used English "name", which is shown in brackets after the reference.
______________________________________ Signal Definition ______________________________________ OE (Output Enable) Opens the data bus buffer of a peripheral device in order for the peripheral device to be able to feed data to the data bus WE (Write Enable) A signal which enables data to be written to a peripheral device CE (Chip Enable) A peripheral device selection signal by which one peripheral device at a time is se1ected to be active ______________________________________
In addition, FIG. 1 shows a clock signal CLK and a WAIT signal, and a control signal STB, the meaning of which will be explained below.
Signals OE are occasionally also referred to by an alternative abbreviation RD (i.e. Read; the microprocessor reads from a peripheral device), and signals WE, correspondingly, by an abbreviation WR (i.e. Write; the microprocessor writes to a peripheral device). When a signal WE is valid, desired data must appear in the inputs of the input register of the peripheral device, and when the signal WE is negated, the desired data remains in the peripheral device (i.e. the new data visible in the inputs is no longer able to be written to the peripheral device).
Selection signals CE are typically generated by combination logic in the decoder 13 from the address appearing over the address bus 11, i.e. the signals CE are activated according to the address appearing over the address bus. A certain address range thus corresponds to each peripheral device in such a manner that when the address is located in this range, a corresponding selection signal CEn (n=1, 2, 3 or 4, depending on which peripheral device is concerned) is active.
Whether it is necessary to generate selection signals CE at all depends on the type of the peripheral device. For instance in peripheral devices wherein only one register is provided, such registers being for instance LED control registers, mere OE and WE signals are required.
When selection signals CEn are used (as is done in the exemplifying case of FIG. 1), the OE and WE signals generated by the microprocessor 10 are applied directly to input pins of the peripheral devices A . . . D corresponding to them.
In the known solution described above, the timing of read and write signals (timing refers to the occurring moments of the rising and/or falling edges of signals, i.e. to the duration of pulses) can be changed only by means of the waiting procedure described above, i.e. by extending the duration of pulses by a certain number of clock cycles by means of control carried out by a WAIT signal.
In the environment described above, it is sometimes problematic as to how the timing requirements of a peripheral device are adapted to those of the microprocessor. This applies especially to writing performed to the peripheral device, since writing takes place on the terms of the peripheral device. As for reading, it is not usually problematic, since it takes place on the terms of the microprocessor. A peripheral device may for instance require a very long address hold time. An address hold time is illustrated in FIG. 2, which shows an address signal ADDR appearing over the bus 12 and a signal WE controlling writing. An address hold time is the time T for which the address ADDR must be active even after the signal WE has been negated (a signal is valid when it is in a logical "0" state). In FIG. 2, a reference symbol ti indicates the moment at which the signal WE is negated, and a reference symbol t2 indicates the moment at which the address is deactivated. An address hold time is sometimes defined also in relation to a selection signal CE in the data books of circuit manufacturers. If hold time requirements are defined in relation to both signals (WE and CE), both requirements must naturally be fulfilled.
Different peripheral devices have different requirements as to how long the address hold time should at least be. These different requirements are due to structural differences between peripheral devices (for instance signal transmission time differences within a peripheral device). A long address hold time cannot however be implemented with the wait state solution described above, because the difference between the moments t1 and t2 generated by the microprocessor will be fixed (constant) in any case.
The problem described above is solved in the known solutions (FIG. 1 is further referred to) by arranging a latch circuit 14 between the microprocessor and a peripheral circuit, and applying the address signal ADDR to the latch circuit. In practice, the latch circuit is a register in which the address is stored until a new address value is applied to the register by means of a separate control signal STB. The control signal is formed from the selection signals CE3 and CE4 of the peripheral devices concerned (in this example, n=3 and n=4, corresponding to the "slow" peripheral devices C and D), which selection signals are connected to the inputs of an AND gate 15. The control signal STB is obtained from the output of the AND gate 15, the control signal being in a logical "0" state when at least one of the selection signals is in a logical "0" state (i.e. is valid) . The signal STB thus determines the moment at which the new address value is stored in the circuit 14, whereby the signal can be used for extending the period for which the address is valid with respect to the peripheral device. In other words, it is a way of extending the address hold time.
However, incorporating a latch circuit and the control required for it in a circuit board renders the practical solution more complicated and thus more expensive. The solution increases especially the number of signal conductors required on the circuit board, which makes circuit board design more difficult.